1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device provided with testing logic circuits which can efficiently implement a function test at a high speed.
2. Description of the Prior Art
FIG. 1 is a block diagram schematically illustrating structure of a conventional semiconductor device. A semiconductor device 1 as shown in FIG. 1 comprises a memory unit 2 formed by four memory blocks 2a, 2b, 2c and 2d which are equal in storage capacity with each other, an address signal decoder circuit 3 for decoding address signals received through address input pins 4 thereby to supply the most significant address internal signal 3b to a nibble control block 7 and other address internal signals 3a to the memory unit 2, a latch circuit 6 for latching input data signals received through a data input pin 5 to supply the latched data signals and reading-writing mode switching signals to the nibble control block 7, the nibble control block 7 whose sequence is controlled by the most significant address signal 3b from the decoder circuit 3 thereby to sequentially write or read data signals in or from the respective memory blocks 2a, 2b, 2c and 2d and an output buffer 9 for outputting output signals from the nibble control block 7 sequentially through a data output pin 10. Now, writing/reading operations of the semiconductor device 1 will be described with reference to FIG. 1.
In a writing operation to the memory unit 2, the data input pin 5 of the semiconductor device 1 receives information signals at "high" or "low" logical levels. The information signals are latched in the latch circuit 6 through an input data bus 5a. The information signals thus latched into the latch circuit 6 are transferred to the I/O-nibble control block 7. The nibble control block 7 enters a writing mode by writing/reading mode switching signals from the latch circuit 6. Further, the decoder circuit 3 supplies the most significant address internal signal 3b in signals obtained by decoding address signals 4a to the nibble control block 7 while supplying other address internal signals 3a to the memory unit 2. The address internal signals 3a other than the most significant one 3b specify one memory cell for each of the memory blocks 2a, 2b, 2c and 2d. In other words, four memory cells are simultaneously selected by the address internal signals 3a. The most significant address internal signal 3b specifies the sequence for writing information signals in the selected four memory cells. The nibble control block 7, the sequence of which is controlled by the most significant address internal signal 3b, sequentially writes the information signals from the latch circuit 6 into the selected four memory cells. The aforementioned sequential operation is generally called as nibble writing.
In the reading operation, the nibble control block 7 enters a reading mode by the writing/reading mode switching signal from the latch circuit 6. The decoder circuit 3 decodes the address signals 4a received through the data input pins 4, thereby to supply the most significant address internal signal 3b to the nibble control block 7 and the other address internal signals 3a to the memory unit 2. The address internal signals 3a other than the most significant one select one memory cell for each of the memory blocks 2a, 2b, 2c and 2d. Since the nibble control block 7 is in the reading mode, the information signals present in the selected four memory cells are simultaneously supplied to the nibble control block 7 through data buses 8a, 8b, 8c and 8d. The most significant address internal signal 3b specifies the sequence for reading the information signals from the memory blocks 2a, 2b, 2c and 2d. The nibble control block 7, the sequence of which is controlled by the most significant address internal signal 3b, sequentially supplies the information signals from the selected four memory cells to the output buffer 9 through a data bus 7a. The output buffer 9 sequentially transfers the received information signals to the data output pin 10. The aforementioned sequential reading operation is generally called as nibble reading.
The function test of a conventional semiconductor device has been performed by employing the above described nibble writing/reading operations sequentially with respect to all of memory cells in a memory unit. In such a conventional method, however, addresses must be specified with respect to all of the memory cells forming the memory unit. Consequently, the time required for the function test is increased following increase in number of the memory cells forming a high-density memory unit, leading to increase in time for identifying the quality of semiconductor devices by function tests in production lines.